ARM Instruction Sets and Processor Architecture

Class: SOC Design & Implementation
Date: 2008/03/06 (Tuesday)
HomePage: My BB
Professor : 朱守禮 (Slo-Li Chu) slchu@cycu.edu.tw
Course Description: ARM Instruction Sets and Processor Architecture.
當天戰鬥力: 90%
吸收度: 80%
Experience:

朱老師的不適合非本課系的人上，要有一定的基礎，而且是有目標的人上，其他的我看上了也沒甚麼用，不是說沒用應該說不合適，講的內容太深入幾近需要實作的人才需要。

本週大綱

1.The Register Banking ! Important !

• There are 7 mode in ARM.
• Data Processing Instruction
• 37 register( CPSR、5SPSR、31GPS ) and PC.

2.CPSR status(NZCVQ ________IFT+MODE).

3.It's different of MIPS and ARM.

• Condition code of every command. ( compiler will get best solution not only branches but all ARM instructions).
• I have try to compile some ARM code by gcc 3.4 of xscal(arm9) , but i didn't see any like "ADDEQ" command.
• Try the command :>armeb-linux-gcc -S t.c -o t.s

for example:

int main(){

int i = 0;

i= ( i ) ? 0 : i * 5;

}