Cpu Design Different

Some questions comes from classmate:

• Single cycle：Basicly one instruction one Cycle, and critical path more long.
  
• Multi cycle：one instruction many Cycle, buf critical path shorter then Single cycle.Using FSM to implement one instruction.

• Break instruction execution into multiple cycles

• One clock cycle for each major task

• Instruction Fetch
• Instruction Decode and Register Fetch
• Execution, memory address computation, or branch computation
• Memory access / R-type instruction completion
• Memory read completion

• Share hardware to simplify datapath。
  

• pipeline：Instruction to go through a several clock. A clock to complete an Instruction, but exception of some special exceptions Instruction.