Interface with methods

Class: SystemVerilog_Verifily
Date: 2008/03/19 (Wen)
HomePage: My BB
Professor : 朱守禮 (Slo-Li Chu) slchu@cycu.edu.tw
Course Description: Interface with methods
當天戰鬥力: 80%
吸收度: 60%
Experience:
Part I: Interface methods( Task/function ) (wrapper ).

• Modports:
• import / export ( import: Interface本身提供Function. export:由外部提供), 想當然爾, export不可合成. import 有條件(如果未用及本身未提供的東西即可).

Ref: System Verilog For Design Page 308.

PartII: Operators

The same as C Language. If got race condition , it synthable but flipflop.

for example: a = a + 1 become a<=a+1;

PartIII: Flow control Instructions:

• fork join( join_any, join_wait, join_all ), disable fork
• for
• while
• case

if control veriable( counter ) not static , it's not synthable!

for example: do{ .... } while( counter <>

remember full case in case block!!

期末作業:
VMM - MIPS lite verification.