System Verilog Instruction introduce.

System Verilog Instruction introduce.
Class: SystemVerilog_Verifily
Date: 2008/03/12 (Wen)
HomePage: My BB
Professor : 朱守禮 (Slo-Li Chu) slchu@cycu.edu.tw
Course Description: System Verilog Instruction introduce.
當天戰鬥力: 80%
吸收度: 20%
Experience:
今天上有關 system verilog instruction, operat, 跟C沒甚麼兩樣, 有在寫應該就都懂.
老師把一些語言定義:

• System Verilog - for verification.
• System C = for Modeling.
• Verilog = for design.

還有提到一些 "Bluespec" <-- 應該是這樣念, 目前沒學到.

其中 struct , union 常用於Interface (使用Packet type).

packet type : reg, bit, byte 這類.

unpacket type : int , integer 這類.

PS1:老師說Subby 適合跑 verification, 我適合寫Modeling.